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【速搜问答】三态逻辑是什么

问答 admin 1个月前 (04-11) 34次浏览 已收录 0个评论

汉英对照:
Chinese-English Translation:

在数字电路中,三态逻辑(英语:Three-state logic)允许输出端在0和1两种逻辑电平之外呈现高阻态,等效于将输出的影响从后级电路中移除。这允许多个电路共同使用同一个输出线(例如总线)。

In digital circuits, three state logic allows the output to present a high resistance state beyond the two logic levels of 0 and 1, which is equivalent to removing the influence of the output from the subsequent circuit. This allows multiple circuits to share the same output line (such as a bus).

在数字电路中,三态逻辑(英语:Three-state logic)允许输出端在 0 和 1 两种逻辑电平之外呈现高阻态,等效于将输出的影响从后级电路中移除。这允许多个电路共同使用同一个输出线(例如总线)。

In digital circuits, three state logic allows the output to present a high resistance state beyond the two logic levels of 0 and 1, which is equivalent to removing the influence of the output from the subsequent circuit. This allows multiple bus lines to be used together, for example.

三态输出在寄存器、总线以及 7400 系列、4000 系列等各型号的逻辑 IC 发挥着重要的作用,并常常内置在其他各种集成电路。除此之外,三态逻辑的典型应用还包括微处理器、存储设备、外设的内部和外部总线。许多设备提供一个 OE(Output Enable)用于在低电平时才令输出使能,而在不使能时保持高阻态。

Tri state output plays an important role in register, bus, 7400 series and 4000 series logic IC, and is often built into other integrated circuits. In addition, typical applications of three state logic include microprocessors, storage devices, internal and external buses of peripherals. Many devices provide an OE (output enable) to enable the output only at low level, while maintaining a high impedance state when not.

不过,三态逻辑(tri-state)这个术语不应该同三值逻辑混淆。

However, the term tri state logic should not be confused with ternary logic.

应用

application

第三状态(Hi-Z)等效于将设备的影响从电路其他部分消除。如果一个或者更多的设备有电气连接,将输出端通过三态逻辑置于高阻态常被用于防止短路。

The third state (Hi-Z) is equivalent to eliminating the influence of the device from other parts of the circuit. If one or more devices have electrical connections, it is often used to prevent short circuit to put the output in high resistance state through three state logic.

三态逻辑缓冲器还可以被用在数据选择器中,尤其是那些具有大量输入的情况。另外,三态逻辑对于总线的工作十分关键。 三态逻辑能够减少用于驱动一系列发光二极管所用的导线数量。

Tri state logic buffers can also be used in data selectors, especially when there are a large number of inputs. In addition, three state logic is very important for the bus. Three state logic can reduce the number of wires used to drive a series of LEDs.

输出选择和芯片选择

Output selection and chip selection

许多设计为连接总线的存储设备(例如 RAM 和 ROM)同时具有 CS(芯片选择,chipselect)和 OE(输出使能,outputenable)引脚,它们起到的作用即产生三态逻辑。如果 CS 未与一个低电平连接,那么将输出高阻态。

Many memory devices (such as RAM and ROM) designed to connect buses have both CS (chip select) and OE (output enable) pins. Their function is to generate three state logic. If the CS is not connected to a low level, a high resistance state will be output.

不同之处在于输出信号所需的时间。当芯片选择未被使能(CS 连接高电平)时,芯片内部根本不工作,并且在提供地址和接收数据之间有显著的时间延迟。当然,这样的优点是在此情况中,芯片所消耗的功率最少。

The difference is the time required to output the signal. When the chip selection is not enabled (CS connection high level), the chip does not work at all, and there is a significant time delay between providing address and receiving data. Of course, the advantage is that in this case, the chip consumes the least power.

当芯片选择连接到一个低电平,那么芯片内部将会进行预设的工作流程,只是因为输出使能引脚未连接低电平,最后并未输出对应的信号。当总线正在进行其他工作的时候,这种特性将会起到作用,而当最后输出使能连接到低电平之后,数据才会以最小延迟的状态输出。具有这样的输出使能引脚的 ROM 或者 SRAM 通常具有两个访问时序:一个是芯片被选择以及地址有效,另一个是输出被使能。

When the chip chooses to connect to a low level, the preset workflow will be carried out inside the chip, just because the output enable pin is not connected to the low level, and the corresponding signal is not output at last. When the bus is in other work, this feature will play a role, and when the final output enable is connected to the low level, the data will be output in the state of minimum delay. A ROM or SRAM with such an output enable pin usually has two access sequences: one is that the chip is selected and the address is valid, and the other is that the output is enabled.

上拉电阻和下拉电阻

Pull up resistance and pull down resistance

主条目:上拉电阻

Main entry: pull up resistor

当一节点所有相连的输出都处于第三状态(高阻态),它们对于电路其余部门的影响就被消除了。如果没有别的电路元素来决定其具体的状态(高或者低),那么其对应的电路节点会处于一种类似“浮动”的状态。电路设计人员经常使用上拉电阻以及下拉电阻(通常为 1 至 100 kΩ)让这个处于三态的节点能有确定的默认逻辑状态,防止状态不定或感染噪声。例如,I²C 总线协议(一种常用的设备间双向通信的协议)在两条通信线上使用了上拉电阻。当设备处于非激活状态,它们“释放”掉通信线并使它们的输出端呈现高阻态,这样使它们的高低电平不影响其他电路。当总线上所有的设备都“释放”掉通信线时,对输出目标电路的唯一影响就是上拉电阻将输出端的电平拉高。当一个设备需要通信时,这个输出端脱离高阻态,并使得通信线的输出端电平降低。这时,通信的设备利用此协议将通信的内容呈现在输出端上——这样将避免总线上一个设备驱动高电平而另一个设备驱动低电平的冲突。

When all the connected outputs of a node are in the third state (high resistance state), their influence on the rest of the circuit is eliminated. If there is no other circuit element to determine its specific state (high or low), then its corresponding circuit node will be in a state similar to “floating”. Circuit designers often use pull-up resistor and pull-down resistor (usually 1 to 100 K Ω) to make the node in three states have a definite default logic state, so as to prevent the node from state uncertainty or noise infection. For example, the I? C bus protocol (a commonly used protocol for two-way communication between devices) uses pull-up resistors on two communication lines. When the devices are inactive, they “release” the communication line and make their output present a high resistance state, so that their high and low levels do not affect other circuits. When all the devices on the bus “release” the communication line, the only influence on the output target circuit is that the pull-up resistor will pull the output level high. When a device needs to communicate, the output is out of the high resistance state, and the output level of the communication line is reduced. At this time, the communication device uses this protocol to present the content of communication on the output end – this will avoid the conflict between one device driving high level and another device driving low level on the bus.

PCI 总线也提供了上拉电阻,但是它们要求在数个时钟周期内将输出信号拉高,为了使得高速工作成为可能,其对应的工作协议要求每一个连接到总线上的设备在至少一个时钟周期的时间里输出控制信号,然后才进入高阻态。这样,上拉电阻的作用只是在面对串扰的情况下,维持总线的信号。

PCI bus also provides pull-up resistance, but they require the output signal to be pulled up in several clock cycles. In order to make high-speed operation possible, the corresponding working protocol requires each device connected to the bus to output the control signal in at least one clock cycle, and then enter the high resistance state. In this way, the pull-up resistor is only used to maintain the bus signal in the face of crosstalk.


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