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【速搜问答】复杂可编程逻辑器件是什么

问答 admin 1个月前 (01-16) 32次浏览 已收录 0个评论

汉英对照:
Chinese-English Translation:

复杂可编程逻辑器件(CPLD)采用CMOS EPROM、EEPROM、快闪存储器和SRAM等编程技术,从而构成了高密度、高速度和低功耗的可编程逻辑器件。

Complex programmable logic device (CPLD) uses CMOS EPROM, EEPROM, flash memory, SRAM and other programming technologies to form a high-density, high-speed and low-power programmable logic device.

CPLD 采用 CMOS EPROM、EEPROM、快闪存储器和 SRAM 等编程技术,从而构成了高密度、高速度和低功耗的可编程逻辑器件。

CPLD adopts CMOS EPROM, EEPROM, flash memory, SRAM and other programming technologies, thus forming a programmable logic device with high density, high speed and low power consumption.

组成

form

CPLD 主要由逻辑块、可编程互连通道和 I/O 块三部分构成。

CPLD is mainly composed of logic block, programmable interconnection channel and I / O block.

规模

scale

CPLD 中的逻辑块类似于一个小规模 PLD,通常一个逻辑块包含 4~20 个宏单元,每个宏单元一般由

The logic block in CPLD is similar to a small-scale PLD. Generally, a logic block contains 4-20 macro units, and each macro unit is composed of two macro units

乘积项阵列、乘积项分配和可编程寄存器构成。每个宏单元有多种配置方式,各宏单元也可级联使用, 因此可实现较复杂组合逻辑和时序逻辑功能。对集成度较高的 CPLD,通常还提供了带片内 RAM/ROM 的嵌入阵列块。

It consists of product term array, product term allocation and programmable register. Each macro unit can be configured in a variety of ways, and each macro unit can also be used in cascade, so it can realize more complex combinational logic and sequential logic functions. For CPLD with high integration, the embedded array block with on-chip RAM / ROM is usually provided.

可编程互连通道主要提供逻辑块、宏单元、输入/输出引脚间的互连网络。输入/输出块(I/O 块)提供内部逻辑到器件 I/O 引脚之间的接口。

Programmable interconnect channel mainly provides the interconnection network among logic block, macro unit and I / O pin. The I / O block provides the interface between the internal logic and the I / O pins of the device.

逻辑规模较大的 CPLD 一般还内带 JTAG 边界扫描测试电路,可对已编程的高密度可编程逻辑器件做全面彻底的系统测试,此外也可通过 JTAG 接口进行在系统编程。

Generally, CPLD with large logic scale also has JTAG boundary scan test circuit, which can test the programmed high-density programmable logic devices thoroughly. In addition, it can also program in system through JTAG interface.

由于集成工艺、集成规模和制造厂家的不同,各种 CPLD 分区结构、逻辑单元等也有较大的差别。

Due to the differences of integration process, integration scale and manufacturers, the partition structure and logic unit of various CPLDs are also quite different.

可编程互连阵列结构

Programmable interconnect array architecture

EPM7128S 器件

EPM7128S device

(1)EPM7128S 器件基本结构

(1) Basic structure of EPM7128S device

EPM7128S 器件主要由逻辑阵列块 LAB、宏单元、I/O 控制块和可编程互连阵列 PIA 构成。

EPM7128S device is mainly composed of logic array block lab, macro unit, I / O control block and programmable interconnect array pia.

在多阵列矩阵结构中,每个宏单元有一个可编程的与阵列和一个固定的或阵列, 以及一个具有独立可编程时钟、时钟使能、清除和置位功能的可配置触发器。每 16 个宏单元组成一组,构成一个灵活的逻辑阵列模块 LAB。多个 LAB 通过可编程互连阵列 PIA 和全局总线相连。每个 LAB 还与相应的 I/O 控制模块相连,以提供直接的输入和输出通道。

In the multi array matrix architecture, each macrocell has a programmable and array, a fixed or array, and a configurable trigger with independent programmable clock, clock enable, clear and set functions. Every 16 macro cells form a group to form a flexible logic array module lab. Multiple lab are connected with global bus through programmable interconnect array pia. Each lab is also connected to the corresponding I / O control module to provide direct input and output channels.

(2)EPM7128S 宏单元结构

(2) EPM7128S macrocell structure

EPM7128S 的每个宏单元能够单独配置为组合逻辑或时序逻辑工作方式。宏单元主要由逻辑阵列、乘积项选择矩阵和可编程寄存器 3 部分组成。可编程寄存器根据逻辑需要,可以编程旁路,实现组合逻辑。如作为寄存器使用,则相应的可编程逻辑器件开发软件将根据设计逻辑需要,选择有效的寄存器工作方式,以使设计所用器件资源最少。

Each macro unit of EPM7128S can be configured as combinational logic or sequential logic. Macro unit is mainly composed of logic array, product selection matrix and programmable register. According to the logic needs, programmable registers can be programmed to bypass and realize combinational logic. If it is used as a register, the corresponding PLD development software will select an effective register working mode according to the design logic needs, so as to minimize the device resources used in the design.

XCR3064XL 器件

Xcr3064xl device

(1)XCR3064XL 器件结构

(1) Xcr3064xl device structure

XCR3064XL 器件宏单元结构,由零功率互连阵列连接起来的功能块及 I/O 单元构成,每个逻辑块含 16 个宏单元。

Xcr3064xl device macrocell structure is composed of function blocks and I / O units connected by zero power interconnection array. Each logic block contains 16 macrocells.

全局互连结构 CPLD

Global interconnect structure CPLD

ispLSI1032 器件结构

IspLSI1032 device structure

ispLSI1032 器件主要由全局布线区 GRP、通用逻辑块 GLB、输入/输出单元 IOC、输出布线区 ORP 和时钟分配网络 CDN 构成。

IspLSI1032 device is mainly composed of GRP, GLB, IOC, ORP and CDN.

通用逻辑块 GLB

General logic block GLB

通用逻辑块 GLB 主要用于实现逻辑功能,GLB 主要由与阵列、乘积项共享阵列、4 输出逻辑宏单元和控制逻辑电路组成。

The general logic block GLB is mainly used to realize logic functions. GLB is mainly composed of shared array with array, product item, 4-output logic macro unit and control logic circuit.

应用

application

基于 SRAM(静态随机存储器)的可重配置 PLD(可编程逻辑器件)的出现,为系统设计者动态改变运行电路中 PLD 的逻辑功能创造了条件。PLD 使用 SRAM 单元来保存配置数据。这些配置数据决定了 PLD 内部的互连关系和逻辑功能,改变这些数据,也就改变了器件的逻辑功能。由于 SRAM 的数据是易失的,因此这些数据必须保存在 PLD 器件以外的 EPROM、EEPROM 或 FLASH ROM 等非易失存储器内,以便使系统在适当的时候将其下载到 PLD 的 SRAM 单元中,从而实现在电路可重配置 ICR(In-Circuit Reconfigurability)。

The appearance of reconfigurable PLD (programmable logic device) based on SRAM (static random access memory) creates conditions for system designers to dynamically change the logic function of PLD in operating circuit. PLD uses SRAM cells to store configuration data. These configuration data determine the interconnection relationship and logic function of PLD. Changing these data will change the logic function of the device. Because the data of SRAM is volatile, these data must be stored in non-volatile memory such as EPROM, EEPROM or Flash ROM outside PLD device, so that the system can download them to SRAM cell of PLD at appropriate time, so as to realize in circuit Reconfigurability (ICR).


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