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【速搜问答】收发器是什么

问答 admin 1个月前 (01-16) 33次浏览 已收录 0个评论

汉英对照:
Chinese-English Translation:

收发器是信号转换的一种装置,通常是指光纤收发器。 光纤收发器的出现,将双绞线电信号和光信号进行相互转换,确保了数据包在两个网络间顺畅传输,同时它将网络的传输距离极限从铜线的100米扩展到100公里(单模光纤)。

Transceiver is a signal conversion device, usually refers to optical fiber transceiver. The appearance of optical fiber transceiver transforms the electrical signal and optical signal of twisted pair to ensure the smooth transmission of data packets between the two networks. At the same time, it expands the transmission distance limit of the network from 100 meters of copper wire to 100 kilometers (single-mode optical fiber).

收发器是信号转换的一种装置,通常是指光纤收发器。 光纤收发器的出现,将双绞线电信号和光信号进行相互转换,确保了数据包在两个网络间顺畅传输,同时它将网络的传输距离极限从铜线的 100 米扩展到 100 公里(单模光纤)。

Transceiver is a signal conversion device, usually refers to optical fiber transceiver. The appearance of optical fiber transceiver transforms the electrical signal and optical signal of twisted pair to ensure the smooth transmission of data packets between the two networks. At the same time, it expands the transmission distance limit of the network from 100 meters of copper wire to 100 kilometers (single-mode optical fiber).

产品介绍

Product introduction

随着技术的不断发展,高速串行 VO 技术取代传统并行 I/O 技术已经成为当前趋势。并行总线接口速度最快为 ATA7 的 133 MB/s,2003 年发布 SATA1. 0 规格提供的传输率就已经达到了 150 MB/s, SATA3. 0 理论速度更是达到了 600 MB/s 的速度,设备工作在高速时,并行总线容易遭受干扰和串扰,使得布线相当复杂。而串行收发器的运用能简化布局设计,减少连接器数量。在具有相同的总线频宽时,串行接口的功耗也比并行端口小。并且设备工作模式从并行传输转变为串行传输,串行的速度就可以随着频率的提高而成倍的提高。

With the continuous development of technology, high-speed serial VO technology to replace the traditional parallel I / O technology has become the current trend. The fastest speed of parallel bus interface is 133 MB / s of ATA7. The transmission rate provided by sata1.0 specification released in 2003 has reached 150 MB / s, and the theoretical speed of sata3.0 has reached 600 MB / s. when the equipment works at high speed, the parallel bus is prone to interference and crosstalk, which makes the wiring quite complex. The use of serial transceiver can simplify the layout design and reduce the number of connectors. With the same bus bandwidth, the power consumption of serial port is smaller than that of parallel port. And the working mode of the device changes from parallel transmission to serial transmission, and the speed of serial transmission can be doubled with the increase of frequency.

基于 FPGA 具有嵌入式 Gb 速率级别以及低功耗架构优点,它能使得设计师利用高效率的 EDA 工具快速解决协议和速率的变化问题。随着 FPGA 的广泛应用,收发器整合在 FPGA 中,成为解决设备传输速度问题的一个有效办法。

FPGA has the advantages of embedded GB rate level and low-power architecture, which enables designers to use efficient EDA tools to quickly solve the problem of protocol and rate changes. With the wide application of FPGA, transceiver integration in FPGA has become an effective way to solve the problem of equipment transmission speed.

分类

classification

按网管来分,可以分为网管型光纤收发器和非网管型光纤收发器。

According to network management, it can be divided into network management optical fiber transceiver and non network management optical fiber transceiver.

随着网络向着可运营可管理的方向发展,大多数运营商都希望自己网络中的所有设备均能做到可远程网管的程度,光纤收发器产品与交换机、路由器一样也逐步向这个方向发展。大多数厂商的网管系统都是基于 SNMP 网络协议上开发的,支持包括 Web、Telnet、CLI 等多种管理方式。管理内容多包括配置光纤收发器的工作模式,监视光纤收发器的模块类型、工作状态、机箱温度、电源状态、输出电压和输出光功率等等。随着运营商对设备网管的需求愈来愈多,相信光纤收发器的网管将日趋实用和智能。

With the development of network towards the direction of operation and management, most operators hope that all devices in their network can be remotely managed. Optical transceiver products, like switches and routers, are gradually developing in this direction. The network management systems of most manufacturers are developed based on SNMP network protocol, and support a variety of management methods, including web, Telnet, CLI and so on. The management content includes configuring the working mode of optical fiber transceiver, monitoring the module type, working status, chassis temperature, power status, output voltage and output optical power of optical fiber transceiver, etc. With the increasing demand of operators for equipment network management, it is believed that the network management of optical fiber transceiver will become more practical and intelligent.

光纤收发器在数据传输上打破了以太网电缆的百米局限性,依靠高性能的交换芯片和大容量的缓存,在真正实现无阻塞传输交换性能的同时,还提供了平衡流量、隔离冲突和检测差错等功能,保证数据传输时的高安全性和稳定性。因此在很长一段时间内光纤收发器产品仍将是实际网络组建中不可缺少的一部分,今后的光纤收发器会朝着高智能、高稳定性、可网管、低成本的方向继续发展。

Fiber optic transceiver breaks the 100 meter limitation of Ethernet cable in data transmission. Relying on high-performance switching chip and large capacity cache, it can truly achieve non blocking transmission switching performance, and at the same time, it also provides functions such as balancing traffic, isolating conflicts and detecting errors, so as to ensure high security and stability in data transmission. Therefore, for a long time, optical fiber transceiver products will still be an indispensable part of the actual network construction. In the future, optical fiber transceiver will continue to develop in the direction of high intelligence, high stability, manageability and low cost.

关键技术

key technology

1.信号完整性

1. Signal integrity

收发器中的锁相环(PLL , phase locked loop ) , CDR(clock and data recovery) ,8B/10B 编解码器等各个混合信号模块设计中有模拟信号,如 PLL 中的压控振荡器,也有数字信号,如 PLL 中的分频器等。在一个芯片中,同时存在模拟和数字信号,容易产生电源同步噪声、地反弹和信号串扰。并且收发器的更高数据率意味着非理想的传输线效应会使布线更加困难,各层中的铜线会产生“趋肤效应”,高频信号掠过导体的表面,增加了信号衰减。

There are analog signals in the design of PLL, CDR, 8B / 10B codec and other mixed signal modules in transceiver, such as voltage controlled oscillator in PLL, and digital signals, such as frequency divider in PLL. In a chip, there are analog and digital signals at the same time, which are easy to produce power synchronization noise, ground bounce and signal crosstalk. And the higher data rate of transceiver means that the non ideal transmission line effect will make the wiring more difficult. The copper wire in each layer will produce “skin effect”, and the high frequency signal will sweep over the surface of the conductor, increasing the signal attenuation.

2.抖动性

2. Jitter

抖动性,是衡量收发器健壮性的最重要参数,因为抖动性直接反映到收发器的误码率。影响抖动性的因素有电源和地的布局、校准电路、封装特性等,其中最主要是 PLL 产生的高速时钟。PLL 对于时钟与数据恢复(CDR)非常重要,PLL 由输人参考时钟驱动,因此参考时钟输人需要满足严格的电器和抖动要求。

Jitter is the most important parameter to measure the robustness of transceiver, because jitter directly reflects the BER of transceiver. The factors that affect the jitter include the layout of power supply and ground, calibration circuit, packaging characteristics, etc. PLL is very important for clock and data recovery (CDR). PLL is driven by the input reference clock, so the reference clock input needs to meet the strict requirements of electrical appliances and jitter.

3.均衡技术

3. Equalization technology

在信道中传输的数据不可避免产生码间干扰和各种噪声影响。在高速速率的情况下,其干扰会更加明显。为了克服传输干扰和损耗,在收发器系统中插入均衡器,经过均衡修正,可以校正和补偿系统特性,减少码间干扰影响,从而能适应信道的随机变化。

The data transmitted in the channel will inevitably produce inter symbol interference and various noise effects. In the case of high speed, the interference will be more obvious. In order to overcome the transmission interference and loss, an equalizer is inserted into the transceiver system. After equalization correction, the system characteristics can be corrected and compensated, and the influence of inter symbol interference can be reduced, so as to adapt to the random changes of the channel.

4.预加重技术

4. Pre weighting technology

在 Gb 级别速率时,设计人员无法简单地通过放大信号解决信号损失问题,因为这将增大功耗并引起眼图的闭合。在布局上,反射能量的强度呈现出近端的不连续性。预加重技术可以透过加重任何信号变化后的第一个数据符号来对发射信号进行预失真处理,消除信道中脉冲响应的前端过冲和后沿拖尾。

At GB rate, the designer can’t solve the problem of signal loss simply by amplifying the signal, because it will increase the power consumption and cause the eye diagram to close. In the layout, the intensity of reflected energy shows a discontinuity at the near end. The pre emphasis technique can pre distort the transmitted signal by adding the first data symbol after any signal changes, so as to eliminate the front-end overshoot and trailing edge of the impulse response in the channel.

系统硬件组成

System hardware composition

每一路高速收发器包括发送器和接收器两个通道,发送器和接收器都是由物理编码子层(PCS,p 场 si-cal coding sublayer)与物理介质附加子层(PMA , physi-cal media additional sublayer)两部分组成。

Each high-speed transceiver includes two channels: transmitter and receiver, which are composed of PCs (P-field Si cal coding sublayer) and PMA (physical medical additional sublayer).

PCS 包括兼容所支持协议的收发器中的数字功能的硬核逻辑实现,发送通道包括相位补偿 FIFO、字节串行器、8B/10B 编码器等模块;接收通道包括字对齐器、速率匹配 FIFO,8B/10B 解码器、字节解串器、字节排序器、相位补偿 FIFO 等模块。

PCs includes the hard core logic implementation of digital functions in transceivers compatible with the supported protocols. The sending channel includes phase compensation FIFO, byte serializer, 8B / 10B encoder and other modules; the receiving channel includes word aligner, rate matching FIFO, 8B / 10B decoder, byte deserializer, byte sequencer, phase compensation FIFO and other modules.

PMA 包括 I/O 缓冲器的模拟电路、CDR、串行器/解串器(SER/DES 以及用于优化串行数据通道性能的可编程预加重与均衡。

PMA includes analog circuit of I / O buffer, CDR, Ser / DES and programmable pre emphasis and equalization to optimize the performance of serial data channel.

设备收发器通道工作时,FPGA 架构中的输出并行数据通过发送器 PCS 和 PMA 进行传输,最终转化为串行数据发送出去。接收到的输人串行数据通过接收器 PMA 和 PCS 的处理以串行数据格式传输到 FP 以架构内部中,进行下一步的处理。

When the transceiver channel works, the output parallel data in FPGA architecture is transmitted through the transmitter PCs and PMA, and finally converted into serial data to be sent out. The received input serial data is processed by PMA and PCs of the receiver and transmitted to FP in serial data format for further processing.

FPGA 集成

FPGA integration

高速收发器的应用广泛,以基于 FPGA 的 SATA 接口固态硬盘为例,SATA 接口固态盘是未来趋势的发展,而高速串行收发器实现了 SATA 的 IP 核存储方式,高速收发器是 SATA 协议中物理层实现的关键部件。SATA 协议串行数据工作在 1.5-6Gbit/s 传输速率上,这是 FPGA 无法直接实现的,为了满足这种需求,许多 FPGA 生产商将通用的高速物理器件集成在 FPGA 内部,并提供灵活的配置方式来完成许多类似的功能。

High speed transceiver is widely used. Taking the solid state disk with SATA interface based on FPGA as an example, the solid state disk with SATA interface is the development trend in the future. The high-speed serial transceiver realizes the IP core storage mode of SATA, and the high-speed transceiver is the key component of the physical layer implementation of the SATA protocol. Serial data of SATA protocol works at 1.5-6gbit/s transmission rate, which can not be directly realized by FPGA. In order to meet this demand, many FPGA manufacturers integrate general high-speed physical devices into FPGA and provide flexible configuration to complete many similar functions.

总结

summary

高速收发器使大量数据点对点进行传输成为可能,这种串行通信技术充分利用传输媒体的信道容量,与并行数据总线相比,减少了所需的传输信道和器件引脚数目,从而大大降低通信成本。一个性能优秀的收发器应具备低功耗、小尺寸、易配置、高效率等优点,以使其容易集成到总线系统中。在高速串行数据传输协议中,收发器的性能对总线接口传输速率起着决定性的作用,也在一定程度上影响了该种总线接口系统的性能。本研究解析了高速收发器模块在 FPGA 平台上的实现,也为各种高速串行协议的实现提供了有益的参考。

High speed transceiver makes it possible to transmit a large amount of data point to point. This serial communication technology makes full use of the channel capacity of the transmission media, reduces the number of transmission channels and device pins required compared with parallel data bus, thus greatly reducing the communication cost. An excellent transceiver should have the advantages of low power consumption, small size, easy configuration and high efficiency, so that it can be easily integrated into the bus system. In the high-speed serial data transmission protocol, the performance of transceiver plays a decisive role in the transmission rate of bus interface, and also affects the performance of the bus interface system to a certain extent. This study analyzes the implementation of high-speed transceiver module on FPGA platform, and also provides a useful reference for the implementation of various high-speed serial protocols.


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